Name: Zhaolin Li

Title: Professor

Email: lzl73@mail.tsinghua.edu.cn

Education

B.Eng. in Semiconductor Physics, Harbin Institute of Technology, 1994.

Ph.D. in Computer Science, Harbin Institute of Technology, 2000.

Services

Chief Expert of the National New Energy Vehicle Technology Innovation Center

Areas of Research Interests/ Research Projects

Multi-core Processors, Parallel Programming and Compilation Optimization, Intelligent Processors

Key R&D Program Project of the Ministry of Science and Technology, Research on Key Technologies of Basic Software and Hardware Systems for Intelligent New Energy Vehicle Onboard Control (2020-2023)

Research Summary

I have undertaken more than 20 projects, including the National Key R&D Program, the National Natural Science Foundation of China, and the 863 Program. I have published over 120 papers in IEEE TPDS, IEEE TVLSI, MICRO, etc., authorized 12 invention patents, formulated more than 30 standards, and authored 4 works. In terms of multi-core processor design, I have proposed various high computing unit utilization compilation optimization techniques and core mapping scheduling methods for VLIW multi-core stream architecture and perception of computing unit utilization, which can optimize the utilization of core computing units, significantly improve processor performance, reduce processor power consumption, and solve the technical problem of high-performance and low-power compilation optimization for multi-core processors based on network on chip.  In terms of parallel programming and compilation optimization, I have proposed a multi task collaborative development method based on micro kernels and computing array engines. For the first time, a configurable software development tool for heterogeneous multi-core architecture has been implemented, solving technical challenges such as heterogeneous multi-core communication, distributed memory management, and cross core task scheduling.  In terms of intelligent processor architecture, I have proposed a new type of ReRAM based LSTM accelerator architecture. By using neural network approximators to achieve vector computation in LSTM, multiple functional units in the system have a consistent architecture, optimizing hardware overhead for analog-to-digital and analog-to-digital conversion, and improving system computational efficiency.

Honors and Awards

First Prize of Technological Invention Award for Outstanding Scientific Research Achievements in Higher Education Institutions (2019)

First Prize for Technological Invention of the China Electronics Society (2017)

Publications

[1] Han, Jianhui; Wang, Mingyu; Liu, He; Li, Zhaolin; Zhang, Youhui. ERA-LSTM: An Efficient ReRAM-Based Architecture for Long Short-Term Memory，IEEE Transactions on Parallel and Distributed Systems, 2020, Vol.31,No.6，p1328-1342.

[2] Mingyu Wang, Zhaolin Li. A Spatial and Temporal Locality-Aware Adaptive Cache Design With Network Optimization for Tiled Many-Core Architectures，IEEE Transactions on Very Large Scale Integration Systems，2017, Vol25, No.9, p2419-2433.

[3] Guoyue Jiang, Zhaolin Li, Fang Wang, Shaojun Wei. A low-latency and low-power hybrid scheme for on-chip networks. IEEE Transactions on Very Large Scale Integration Systems, 2015, Vol.23, No.4, p664-677.

[4] Shan Cao, Zhaolin Li, Fang Wang, Shaojun Wei. Compiler-assisted leakage- and temperature-aware instruction-level VLIW scheduling. IEEE Transactions on Very Large Scale Integration Systems, 2014, Vol.22, No.6, p1416-1428.

[5] Guoyue Jiang, Zhaolin Li, Fang Wang, Shaojun Wei. A high-utilization scheduling scheme of stream programs on clustered VLIW stream architectures. IEEE Transactions on Parallel and Distributed Systems, 2014, Vol.25, No.4, p840-850.

[6] Li Zhaolin, Wang Mingyu, and Wei Shaojun, "Multi Core Processors - Principles, Design, and Optimization," Tsinghua University Press, February 2021